Flashing Uboot to MMC

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Exact process of flashing Uboot to MMC.

  • For now flashed uboot wont start
    • Uboot start when flashed from running system

Prerequisites

BCT Creation process

Your currect BCT can be extracted with tegrarcm or nvflash.

Extract bct and bootloader (tegrarcm)

sudo tegrarcm readbct --bct=ac100.bct

Extract 0 to 1536 sectors of your mmc (nvflash)

nvflash --bl fastboot.bin --rawdeviceread 0 1536 ac100-part-2.img --go

Extract 4080 bytes of that image which contain bct and bootloader (nvflash)

dd if=ac100-part-2.img of=ac100.bct bs=4080 count=1

Decode bct with bct_dump

  • Optional step only to check that bct correct, fresh cbootimage dont need decoded bct to create new
bct_dump ac100.bct > ac100.bct.cfg
    • My decoded bct (ac100-116 32gb,bt,3g)
Version       = 0x00020001;
BlockSize     = 0x00004000;
PageSize      = 0x00000200;
PartitionSize = 0x01000000;
OdmData       = 0x800c0075;

# Bootloader used       = 0;
# Bootloaders max       = 4;
# BCT size              = 4080;
# Hash size             = 16;
# Crypto offset         = 16;
# Crypto length         = 4064;
# Max BCT search blocks = 64;

DevType[0] = NvBootDevType_Sdmmc;
DeviceParam[0].SdmmcParams.ClockDivider           = 0x0000000c;
DeviceParam[0].SdmmcParams.DataWidth              = NvBootSdmmcDataWidth_8Bit;
DeviceParam[0].SdmmcParams.MaxPowerClassSupported = 0x00000000;

DevType[1] = NvBootDevType_Sdmmc;
DeviceParam[1].SdmmcParams.ClockDivider           = 0x0000000c;
DeviceParam[1].SdmmcParams.DataWidth              = NvBootSdmmcDataWidth_8Bit;
DeviceParam[1].SdmmcParams.MaxPowerClassSupported = 0x00000000;

DevType[2] = NvBootDevType_Sdmmc;
DeviceParam[2].SdmmcParams.ClockDivider           = 0x0000000c;
DeviceParam[2].SdmmcParams.DataWidth              = NvBootSdmmcDataWidth_8Bit;
DeviceParam[2].SdmmcParams.MaxPowerClassSupported = 0x00000000;

DevType[3] = NvBootDevType_Sdmmc;
DeviceParam[3].SdmmcParams.ClockDivider           = 0x0000000c;
DeviceParam[3].SdmmcParams.DataWidth              = NvBootSdmmcDataWidth_8Bit;
DeviceParam[3].SdmmcParams.MaxPowerClassSupported = 0x00000000;

SDRAM[0].MemoryType                 = NvBootMemoryType_Ddr2;
SDRAM[0].PllMChargePumpSetupControl = 0x00000008;
SDRAM[0].PllMLoopFilterSetupControl = 0x00000000;
SDRAM[0].PllMInputDivider           = 0x0000000c;
SDRAM[0].PllMFeedbackDivider        = 0x0000029a;
SDRAM[0].PllMPostDivider            = 0x00000000;
SDRAM[0].PllMStableTime             = 0x0000012c;
SDRAM[0].EmcClockDivider            = 0x00000001;
SDRAM[0].EmcAutoCalInterval         = 0x00000000;
SDRAM[0].EmcAutoCalConfig           = 0xe0a61111;
SDRAM[0].EmcAutoCalWait             = 0x00000000;
SDRAM[0].EmcPinProgramWait          = 0x00000000;
SDRAM[0].EmcRc                      = 0x00000014;
SDRAM[0].EmcRfc                     = 0x0000002b;
SDRAM[0].EmcRas                     = 0x0000000f;
SDRAM[0].EmcRp                      = 0x00000005;
SDRAM[0].EmcR2w                     = 0x00000004;
SDRAM[0].EmcW2r                     = 0x00000005;
SDRAM[0].EmcR2p                     = 0x00000003;
SDRAM[0].EmcW2p                     = 0x0000000c;
SDRAM[0].EmcRrd                     = 0x00000003;
SDRAM[0].EmcRdRcd                   = 0x00000005;
SDRAM[0].EmcWrRcd                   = 0x00000005;
SDRAM[0].EmcRext                    = 0x00000001;
SDRAM[0].EmcWdv                     = 0x00000004;
SDRAM[0].EmcQUseExtra               = 0x00000000;
SDRAM[0].EmcQUse                    = 0x00000005;
SDRAM[0].EmcQRst                    = 0x00000004;
SDRAM[0].EmcQSafe                   = 0x00000009;
SDRAM[0].EmcRdv                     = 0x0000000d;
SDRAM[0].EmcRefresh                 = 0x000009ff;
SDRAM[0].EmcBurstRefreshNum         = 0x00000000;
SDRAM[0].EmcPdEx2Wr                 = 0x00000003;
SDRAM[0].EmcPdEx2Rd                 = 0x00000003;
SDRAM[0].EmcPChg2Pden               = 0x00000005;
SDRAM[0].EmcAct2Pden                = 0x00000005;
SDRAM[0].EmcAr2Pden                 = 0x00000001;
SDRAM[0].EmcRw2Pden                 = 0x0000000f;
SDRAM[0].EmcTxsr                    = 0x000000c8;
SDRAM[0].EmcTcke                    = 0x00000003;
SDRAM[0].EmcTfaw                    = 0x0000000c;
SDRAM[0].EmcTrpab                   = 0x00000006;
SDRAM[0].EmcTClkStable              = 0x00000008;
SDRAM[0].EmcTClkStop                = 0x00000002;
SDRAM[0].EmcTRefBw                  = 0x00000000;
SDRAM[0].EmcFbioCfg1                = 0x00000000;
SDRAM[0].EmcFbioDqsibDlyMsb         = 0x00000000;
SDRAM[0].EmcFbioDqsibDly            = 0x34343434;
SDRAM[0].EmcFbioQuseDlyMsb          = 0x00000000;
SDRAM[0].EmcFbioQuseDly             = 0x6c6c6c6c;
SDRAM[0].EmcFbioCfg5                = 0x00000083;
SDRAM[0].EmcFbioCfg6                = 0x00000002;
SDRAM[0].EmcFbioSpare               = 0x00000000;
SDRAM[0].EmcMrsResetDllWait         = 0x00000000;
SDRAM[0].EmcMrsResetDll             = 0x00000000;
SDRAM[0].EmcMrsDdr2DllReset         = 0x00000100;
SDRAM[0].EmcMrs                     = 0x00000a6a;
SDRAM[0].EmcEmrsEmr2                = 0x00200000;
SDRAM[0].EmcEmrsEmr3                = 0x00300000;
SDRAM[0].EmcEmrsDdr2DllEnable       = 0x00100000;
SDRAM[0].EmcEmrsDdr2OcdCalib        = 0x00100382;
SDRAM[0].EmcEmrs                    = 0x00100002;
SDRAM[0].EmcMrw1                    = 0x00000000;
SDRAM[0].EmcMrw2                    = 0x00000000;
SDRAM[0].EmcMrw3                    = 0x00000000;
SDRAM[0].EmcMrwResetCommand         = 0x00000000;
SDRAM[0].EmcMrwResetNInitWait       = 0x00000000;
SDRAM[0].EmcAdrCfg1                 = 0x00070303;
SDRAM[0].EmcAdrCfg                  = 0x00070303;
SDRAM[0].McEmemCfg                  = 0x00080000;
SDRAM[0].McLowLatencyConfig         = 0x80000003;
SDRAM[0].EmcCfg2                    = 0x00000405;
SDRAM[0].EmcCfgDigDll               = 0x00000016;
SDRAM[0].EmcCfgClktrim0             = 0x00000000;
SDRAM[0].EmcCfgClktrim1             = 0x00000000;
SDRAM[0].EmcCfgClktrim2             = 0x00000000;
SDRAM[0].EmcCfg                     = 0x0001ff00;
SDRAM[0].EmcDbg                     = 0x01000000;
SDRAM[0].AhbArbitrationXbarCtrl     = 0x00010000;
SDRAM[0].EmcDllXformDqs             = 0x00000010;
SDRAM[0].EmcDllXformQUse            = 0x00000008;
SDRAM[0].WarmBootWait               = 0x00000002;
SDRAM[0].EmcCttTermCtrl             = 0x00000802;
SDRAM[0].EmcOdtWrite                = 0x00000000;
SDRAM[0].EmcOdtRead                 = 0x00000000;
SDRAM[0].EmcZcalRefCnt              = 0x00000000;
SDRAM[0].EmcZcalWaitCnt             = 0x00000000;
SDRAM[0].EmcZcalMrwCmd              = 0x00000000;
SDRAM[0].EmcMrwZqInitDev0           = 0x00000000;
SDRAM[0].EmcMrwZqInitDev1           = 0x00000000;
SDRAM[0].EmcMrwZqInitWait           = 0x00000000;
SDRAM[0].EmcDdr2Wait                = 0x00000002;
SDRAM[0].PmcDdrPwr                  = 0x00000001;
SDRAM[0].ApbMiscGpXm2CfgAPadCtrl    = 0x77ffc000;
SDRAM[0].ApbMiscGpXm2CfgCPadCtrl2   = 0x08080079;
SDRAM[0].ApbMiscGpXm2CfgCPadCtrl    = 0x77fffff0;
SDRAM[0].ApbMiscGpXm2CfgDPadCtrl2   = 0x44440009;
SDRAM[0].ApbMiscGpXm2CfgDPadCtrl    = 0x77fffff0;
SDRAM[0].ApbMiscGpXm2ClkCfgPadCtrl  = 0x77ffc000;
SDRAM[0].ApbMiscGpXm2CompPadCtrl    = 0x01f1f008;
SDRAM[0].ApbMiscGpXm2VttGenPadCtrl  = 0x07076600;

SDRAM[1].MemoryType                 = NvBootMemoryType_Ddr2;
SDRAM[1].PllMChargePumpSetupControl = 0x00000008;
SDRAM[1].PllMLoopFilterSetupControl = 0x00000000;
SDRAM[1].PllMInputDivider           = 0x0000000c;
SDRAM[1].PllMFeedbackDivider        = 0x0000029a;
SDRAM[1].PllMPostDivider            = 0x00000000;
SDRAM[1].PllMStableTime             = 0x0000012c;
SDRAM[1].EmcClockDivider            = 0x00000001;
SDRAM[1].EmcAutoCalInterval         = 0x00000000;
SDRAM[1].EmcAutoCalConfig           = 0xe0a61111;
SDRAM[1].EmcAutoCalWait             = 0x00000000;
SDRAM[1].EmcPinProgramWait          = 0x00000000;
SDRAM[1].EmcRc                      = 0x00000014;
SDRAM[1].EmcRfc                     = 0x0000002b;
SDRAM[1].EmcRas                     = 0x0000000f;
SDRAM[1].EmcRp                      = 0x00000005;
SDRAM[1].EmcR2w                     = 0x00000004;
SDRAM[1].EmcW2r                     = 0x00000005;
SDRAM[1].EmcR2p                     = 0x00000003;
SDRAM[1].EmcW2p                     = 0x0000000c;
SDRAM[1].EmcRrd                     = 0x00000003;
SDRAM[1].EmcRdRcd                   = 0x00000005;
SDRAM[1].EmcWrRcd                   = 0x00000005;
SDRAM[1].EmcRext                    = 0x00000001;
SDRAM[1].EmcWdv                     = 0x00000004;
SDRAM[1].EmcQUseExtra               = 0x00000000;
SDRAM[1].EmcQUse                    = 0x00000005;
SDRAM[1].EmcQRst                    = 0x00000004;
SDRAM[1].EmcQSafe                   = 0x00000009;
SDRAM[1].EmcRdv                     = 0x0000000d;
SDRAM[1].EmcRefresh                 = 0x000009ff;
SDRAM[1].EmcBurstRefreshNum         = 0x00000000;
SDRAM[1].EmcPdEx2Wr                 = 0x00000003;
SDRAM[1].EmcPdEx2Rd                 = 0x00000003;
SDRAM[1].EmcPChg2Pden               = 0x00000005;
SDRAM[1].EmcAct2Pden                = 0x00000005;
SDRAM[1].EmcAr2Pden                 = 0x00000001;
SDRAM[1].EmcRw2Pden                 = 0x0000000f;
SDRAM[1].EmcTxsr                    = 0x000000c8;
SDRAM[1].EmcTcke                    = 0x00000003;
SDRAM[1].EmcTfaw                    = 0x0000000c;
SDRAM[1].EmcTrpab                   = 0x00000006;
SDRAM[1].EmcTClkStable              = 0x00000008;
SDRAM[1].EmcTClkStop                = 0x00000002;
SDRAM[1].EmcTRefBw                  = 0x00000000;
SDRAM[1].EmcFbioCfg1                = 0x00000000;
SDRAM[1].EmcFbioDqsibDlyMsb         = 0x00000000;
SDRAM[1].EmcFbioDqsibDly            = 0x34343434;
SDRAM[1].EmcFbioQuseDlyMsb          = 0x00000000;
SDRAM[1].EmcFbioQuseDly             = 0x6c6c6c6c;
SDRAM[1].EmcFbioCfg5                = 0x00000083;
SDRAM[1].EmcFbioCfg6                = 0x00000002;
SDRAM[1].EmcFbioSpare               = 0x00000000;
SDRAM[1].EmcMrsResetDllWait         = 0x00000000;
SDRAM[1].EmcMrsResetDll             = 0x00000000;
SDRAM[1].EmcMrsDdr2DllReset         = 0x00000100;
SDRAM[1].EmcMrs                     = 0x00000a6a;
SDRAM[1].EmcEmrsEmr2                = 0x00200000;
SDRAM[1].EmcEmrsEmr3                = 0x00300000;
SDRAM[1].EmcEmrsDdr2DllEnable       = 0x00100000;
SDRAM[1].EmcEmrsDdr2OcdCalib        = 0x00100382;
SDRAM[1].EmcEmrs                    = 0x00100002;
SDRAM[1].EmcMrw1                    = 0x00000000;
SDRAM[1].EmcMrw2                    = 0x00000000;
SDRAM[1].EmcMrw3                    = 0x00000000;
SDRAM[1].EmcMrwResetCommand         = 0x00000000;
SDRAM[1].EmcMrwResetNInitWait       = 0x00000000;
SDRAM[1].EmcAdrCfg1                 = 0x00070303;
SDRAM[1].EmcAdrCfg                  = 0x00070303;
SDRAM[1].McEmemCfg                  = 0x00080000;
SDRAM[1].McLowLatencyConfig         = 0x80000003;
SDRAM[1].EmcCfg2                    = 0x00000405;
SDRAM[1].EmcCfgDigDll               = 0x00000016;
SDRAM[1].EmcCfgClktrim0             = 0x00000000;
SDRAM[1].EmcCfgClktrim1             = 0x00000000;
SDRAM[1].EmcCfgClktrim2             = 0x00000000;
SDRAM[1].EmcCfg                     = 0x0001ff00;
SDRAM[1].EmcDbg                     = 0x01000000;
SDRAM[1].AhbArbitrationXbarCtrl     = 0x00010000;
SDRAM[1].EmcDllXformDqs             = 0x00000010;
SDRAM[1].EmcDllXformQUse            = 0x00000008;
SDRAM[1].WarmBootWait               = 0x00000002;
SDRAM[1].EmcCttTermCtrl             = 0x00000802;
SDRAM[1].EmcOdtWrite                = 0x00000000;
SDRAM[1].EmcOdtRead                 = 0x00000000;
SDRAM[1].EmcZcalRefCnt              = 0x00000000;
SDRAM[1].EmcZcalWaitCnt             = 0x00000000;
SDRAM[1].EmcZcalMrwCmd              = 0x00000000;
SDRAM[1].EmcMrwZqInitDev0           = 0x00000000;
SDRAM[1].EmcMrwZqInitDev1           = 0x00000000;
SDRAM[1].EmcMrwZqInitWait           = 0x00000000;
SDRAM[1].EmcDdr2Wait                = 0x00000002;
SDRAM[1].PmcDdrPwr                  = 0x00000001;
SDRAM[1].ApbMiscGpXm2CfgAPadCtrl    = 0x77ffc000;
SDRAM[1].ApbMiscGpXm2CfgCPadCtrl2   = 0x08080079;
SDRAM[1].ApbMiscGpXm2CfgCPadCtrl    = 0x77fffff0;
SDRAM[1].ApbMiscGpXm2CfgDPadCtrl2   = 0x44440009;
SDRAM[1].ApbMiscGpXm2CfgDPadCtrl    = 0x77fffff0;
SDRAM[1].ApbMiscGpXm2ClkCfgPadCtrl  = 0x77ffc000;
SDRAM[1].ApbMiscGpXm2CompPadCtrl    = 0x01f1f008;
SDRAM[1].ApbMiscGpXm2VttGenPadCtrl  = 0x07076600;

SDRAM[2].MemoryType                 = NvBootMemoryType_Ddr2;
SDRAM[2].PllMChargePumpSetupControl = 0x00000008;
SDRAM[2].PllMLoopFilterSetupControl = 0x00000000;
SDRAM[2].PllMInputDivider           = 0x0000000c;
SDRAM[2].PllMFeedbackDivider        = 0x0000029a;
SDRAM[2].PllMPostDivider            = 0x00000000;
SDRAM[2].PllMStableTime             = 0x0000012c;
SDRAM[2].EmcClockDivider            = 0x00000001;
SDRAM[2].EmcAutoCalInterval         = 0x00000000;
SDRAM[2].EmcAutoCalConfig           = 0xe0a61111;
SDRAM[2].EmcAutoCalWait             = 0x00000000;
SDRAM[2].EmcPinProgramWait          = 0x00000000;
SDRAM[2].EmcRc                      = 0x00000014;
SDRAM[2].EmcRfc                     = 0x0000002b;
SDRAM[2].EmcRas                     = 0x0000000f;
SDRAM[2].EmcRp                      = 0x00000005;
SDRAM[2].EmcR2w                     = 0x00000004;
SDRAM[2].EmcW2r                     = 0x00000005;
SDRAM[2].EmcR2p                     = 0x00000003;
SDRAM[2].EmcW2p                     = 0x0000000c;
SDRAM[2].EmcRrd                     = 0x00000003;
SDRAM[2].EmcRdRcd                   = 0x00000005;
SDRAM[2].EmcWrRcd                   = 0x00000005;
SDRAM[2].EmcRext                    = 0x00000001;
SDRAM[2].EmcWdv                     = 0x00000004;
SDRAM[2].EmcQUseExtra               = 0x00000000;
SDRAM[2].EmcQUse                    = 0x00000005;
SDRAM[2].EmcQRst                    = 0x00000004;
SDRAM[2].EmcQSafe                   = 0x00000009;
SDRAM[2].EmcRdv                     = 0x0000000d;
SDRAM[2].EmcRefresh                 = 0x000009ff;
SDRAM[2].EmcBurstRefreshNum         = 0x00000000;
SDRAM[2].EmcPdEx2Wr                 = 0x00000003;
SDRAM[2].EmcPdEx2Rd                 = 0x00000003;
SDRAM[2].EmcPChg2Pden               = 0x00000005;
SDRAM[2].EmcAct2Pden                = 0x00000005;
SDRAM[2].EmcAr2Pden                 = 0x00000001;
SDRAM[2].EmcRw2Pden                 = 0x0000000f;
SDRAM[2].EmcTxsr                    = 0x000000c8;
SDRAM[2].EmcTcke                    = 0x00000003;
SDRAM[2].EmcTfaw                    = 0x0000000c;
SDRAM[2].EmcTrpab                   = 0x00000006;
SDRAM[2].EmcTClkStable              = 0x00000008;
SDRAM[2].EmcTClkStop                = 0x00000002;
SDRAM[2].EmcTRefBw                  = 0x00000000;
SDRAM[2].EmcFbioCfg1                = 0x00000000;
SDRAM[2].EmcFbioDqsibDlyMsb         = 0x00000000;
SDRAM[2].EmcFbioDqsibDly            = 0x34343434;
SDRAM[2].EmcFbioQuseDlyMsb          = 0x00000000;
SDRAM[2].EmcFbioQuseDly             = 0x6c6c6c6c;
SDRAM[2].EmcFbioCfg5                = 0x00000083;
SDRAM[2].EmcFbioCfg6                = 0x00000002;
SDRAM[2].EmcFbioSpare               = 0x00000000;
SDRAM[2].EmcMrsResetDllWait         = 0x00000000;
SDRAM[2].EmcMrsResetDll             = 0x00000000;
SDRAM[2].EmcMrsDdr2DllReset         = 0x00000100;
SDRAM[2].EmcMrs                     = 0x00000a6a;
SDRAM[2].EmcEmrsEmr2                = 0x00200000;
SDRAM[2].EmcEmrsEmr3                = 0x00300000;
SDRAM[2].EmcEmrsDdr2DllEnable       = 0x00100000;
SDRAM[2].EmcEmrsDdr2OcdCalib        = 0x00100382;
SDRAM[2].EmcEmrs                    = 0x00100002;
SDRAM[2].EmcMrw1                    = 0x00000000;
SDRAM[2].EmcMrw2                    = 0x00000000;
SDRAM[2].EmcMrw3                    = 0x00000000;
SDRAM[2].EmcMrwResetCommand         = 0x00000000;
SDRAM[2].EmcMrwResetNInitWait       = 0x00000000;
SDRAM[2].EmcAdrCfg1                 = 0x00070303;
SDRAM[2].EmcAdrCfg                  = 0x00070303;
SDRAM[2].McEmemCfg                  = 0x00080000;
SDRAM[2].McLowLatencyConfig         = 0x80000003;
SDRAM[2].EmcCfg2                    = 0x00000405;
SDRAM[2].EmcCfgDigDll               = 0x00000016;
SDRAM[2].EmcCfgClktrim0             = 0x00000000;
SDRAM[2].EmcCfgClktrim1             = 0x00000000;
SDRAM[2].EmcCfgClktrim2             = 0x00000000;
SDRAM[2].EmcCfg                     = 0x0001ff00;
SDRAM[2].EmcDbg                     = 0x01000000;
SDRAM[2].AhbArbitrationXbarCtrl     = 0x00010000;
SDRAM[2].EmcDllXformDqs             = 0x00000010;
SDRAM[2].EmcDllXformQUse            = 0x00000008;
SDRAM[2].WarmBootWait               = 0x00000002;
SDRAM[2].EmcCttTermCtrl             = 0x00000802;
SDRAM[2].EmcOdtWrite                = 0x00000000;
SDRAM[2].EmcOdtRead                 = 0x00000000;
SDRAM[2].EmcZcalRefCnt              = 0x00000000;
SDRAM[2].EmcZcalWaitCnt             = 0x00000000;
SDRAM[2].EmcZcalMrwCmd              = 0x00000000;
SDRAM[2].EmcMrwZqInitDev0           = 0x00000000;
SDRAM[2].EmcMrwZqInitDev1           = 0x00000000;
SDRAM[2].EmcMrwZqInitWait           = 0x00000000;
SDRAM[2].EmcDdr2Wait                = 0x00000002;
SDRAM[2].PmcDdrPwr                  = 0x00000001;
SDRAM[2].ApbMiscGpXm2CfgAPadCtrl    = 0x77ffc000;
SDRAM[2].ApbMiscGpXm2CfgCPadCtrl2   = 0x08080079;
SDRAM[2].ApbMiscGpXm2CfgCPadCtrl    = 0x77fffff0;
SDRAM[2].ApbMiscGpXm2CfgDPadCtrl2   = 0x44440009;
SDRAM[2].ApbMiscGpXm2CfgDPadCtrl    = 0x77fffff0;
SDRAM[2].ApbMiscGpXm2ClkCfgPadCtrl  = 0x77ffc000;
SDRAM[2].ApbMiscGpXm2CompPadCtrl    = 0x01f1f008;
SDRAM[2].ApbMiscGpXm2VttGenPadCtrl  = 0x07076600;


Create cbootimage config file

For example u-boot.cfg, with this content

# Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
#
# This software is provided 'as-is', without any express or implied
# warranty. In no event will the authors be held liable for any damages
# arising from the use of this software.
#
# Permission is granted to anyone to use this software for any purpose,
# including commercial applications, and to alter it and redistribute it
# freely, subject to the following restrictions:
#
# 1. The origin of this software must not be misrepresented; you must not
#    claim that you wrote the original software. If you use this software
#    in a product, an acknowledgment in the product documentation would be
#    appreciated but is not required.
# 2. Altered source versions must be plainly marked as such, and must not be
#    misrepresented as being the original software.
# 3. This notice may not be removed or altered from any source distribution.

Version       = 0x00020001;
Bctcopy       = 1;
Bctfile       = ac100.bct;
BootLoader    = u-boot.bin,0x00108000,0x00108000,Complete;

Compile new combined bct

cbootimage -d u-boot.cfg ac100.bct.new
  • Output
bct size: 4080
**update_bl()
begin_update(): bct data: b=14 p=9
write_bootloaders()
  redundancy = 1
**BL[0]: 131073 0001 0000 313691 0x00108000 0x00108000 k=a8f61eef01b368ee92e932474a0cee1b
**BL[1]: 0 0000 0000 0000 0x00000000 0x00000000 k=00000000000000000000000000000000
**BL[2]: 0 0000 0000 0000 0x00000000 0x00000000 k=00000000000000000000000000000000
**BL[3]: 0 0000 0000 0000 0x00000000 0x00000000 k=00000000000000000000000000000000
Image file ac100.bct.new has been successfully generated!
    • Output file
330240 Apr 25 13:25 ac100.bct.new

Flash new bct from running system

echo 0 > /sys/block/mmcblk0boot0/force_ro
chmod 666 /dev/block/mmcblk0boot0
dd if=ac100.bct.new of=/dev/block/mmcblk0boot0
echo 1 > /sys/block/mmcblk0boot0/force_ro
  • mmcblk1boot0 with mainline kernels

Successful dd output must look like this

645+0 records in
645+0 records out
330240 bytes transferred in 0.230 secs (1435826 bytes/sec)