Unknown user в 08:15, 15 октября 2014

2014-10-15T08:15:09Z

Новая страница

==Исходники от Toshiba==

https://gitorious.org/ac100/kernel/blobs/toshiba_froyo/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_pinmux_tables.c#line55
<pre>
if (pin_config[0].func == TEGRA_MUX_PLLA_OUT)
ClockFreqInKHz = NvRmPrivGetClockSourceFreq(NvRmClockSource_PllA0);
else if (pin_config[0].func == TEGRA_MUX_OSC)
ClockFreqInKHz = NvRmPrivGetClockSourceFreq(NvRmClockSource_ClkM);
break;
</pre>

https://gitorious.org/ac100/kernel/blobs/toshiba_froyo/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_pinmux_tables.c#line101
NvRmPrivAp20EnableExternalClockSource

https://gitorious.org/ac100/kernel/blobs/toshiba_froyo/arch/arm/mach-tegra/include/nvodm_query_pins_ap20.h#line74
NvOdmPinRegister_Ap20_PadCtrl_CDEV1CFGPADCTRL = 0x20000878UL,

https://gitorious.org/ac100/kernel/blobs/toshiba_froyo/arch/arm/mach-tegra/include/ap20/arapb_misc.h

----

kernel\arch\arm\mach-tegra\odm_kit\query\paz00\subboards\nvodm_query_discovery_e1162_addresses.h
<pre>
// Audio Codec on GEN1_I2C (I2C_1)
static const NvOdmIoAddress s_AudioCodecAddressesI2C_1[] =
{
{ NvOdmIoModule_ExternalClock, 0, 0 }, /* Codec MCLK -> APxx DAP_MCLK1 */
{ NvOdmIoModule_I2c, 0x00, 0x3C }, /* Codec I2C -> APxx PMU I2C, segment 0 */
/* Codec I2C address is 0x3C */
{ NvOdmIoModule_Gpio, (NvU32)'w'-'a', 0x02 }, /* GPIO Port W and Pin 2 for HP_DET */
};
</pre>

kernel\arch\arm\mach-tegra\odm_kit\query\paz00\nvodm_query_pinmux.c
...

kernel\arch\arm\mach-tegra\nvrm\core\ap20\ap20rm_clocks_info.c
<pre>
{ /* I2S1 controller module */
NvRmModuleID_I2s, 0, 0,
{
NvRmClockSource_PllA0,
NvRmClockSource_AudioSync,
NvRmClockSource_PllP0,
NvRmClockSource_ClkM
},
NvRmClockDivider_Fractional_2,
NV_COMMON_CLK_RST_FIELDS_INFO(I2S1, L),
NvRmDiagModuleID_I2s
},

{ /* I2S2 controller module */
NvRmModuleID_I2s, 1, 0,
{
NvRmClockSource_PllA0,
NvRmClockSource_AudioSync,
NvRmClockSource_PllP0,
NvRmClockSource_ClkM
},
NvRmClockDivider_Fractional_2,
NV_COMMON_CLK_RST_FIELDS_INFO(I2S2, L),
NvRmDiagModuleID_I2s
},
</pre>
<pre>
{ /* AC97 controller module */
NvRmModuleID_Ac97, 0, 0,
{
NvRmClockSource_Apb
},
NvRmClockDivider_None,
0, 0, 0, 0, 0,

CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0,
CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_FIELD,
CLK_RST_CONTROLLER_RST_DEVICES_L_0,
CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_FIELD,
NvRmDiagModuleID_Ac97
},
</pre>
<pre>
static const NvRmSelectorClockInfo s_Ap20SelectorClockTable[] =
{
{
NvRmClockSource_AudioSync,
{
NvRmClockSource_ExtSpdf,
NvRmClockSource_ExtI2s1,
NvRmClockSource_ExtI2s2,
NvRmClockSource_ExtAc97,
NvRmClockSource_PllA0,
NvRmClockSource_ExtAudio2,
NvRmClockSource_ExtAudio1,
NvRmClockSource_ExtVi
},
CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0,

CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_RATE_DEFAULT_MASK,
CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_RATE_SHIFT,

CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0,
CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_SYNC_CLK_DOUBLER_ENB_FIELD
},
};

static const NvU32 s_Ap20SelectorClockTableSize = NV_ARRAY_SIZE(s_Ap20SelectorClockTable);
</pre>

arch\arm\mach-tegra\nvrm\core\ap20\ap20rm_clocks_info.c
<pre>
* Notation clarification: in h/w documentation PLL base outputs (except PLLA
* output) are denoted as PllX_OUT0, and the seconadry PLL outputs (if any)
* after fractional dividers are denoted as PllX_OUT1, PllX_OUT2, .... However,
* no h/w name is defined for the base PLLA output, and the output of the PLLA
* secondary divider is marked as PllA_OUT0 (not PllA_OUT1). Threfore, we use
* PllA1 (not PllA0) to denote base PLLA clock.
</pre>

arch\arm\mach-tegra\include\ap20\arclk_rst.h
<pre>
#define CLK_RST_CONTROLLER_PLLA_BASE_0 _MK_ADDR_CONST(0xb0)
...
#define CLK_RST_CONTROLLER_PLLA_OUT_0 _MK_ADDR_CONST(0xb4)
</pre>

Звук. Исходники от Toshiba - История изменений

Unknown user в 08:15, 15 октября 2014