Sound
Datasheet for Realtek ALC5632: ALC5632-GRT.pdf Datasheet for Texas Instruments TPA6017A2 (speakers amplifier): TPA6017a2.pdf paz00: PAZ00 Schematics Document.pdf
Actual values
checked during sound playback: android: MCLK = 11.3 MHz, SDAC=BCLK=2.8 MHz, SDALRCK=44.1 kHz linux: MCLK=absent, SDAC=BCLK=11.3 MHz, SDALRCK=44.1 kHz
cat /sys/kernel/debug/clock/clock_tree
gives in 2.6.38
pll_p_out1 on 2 7.5 28800000
pll_a on 2 x1.9.. 56448000
pll_a_out0 on 3 2.5 22579200
audio on 1 22579200
*audio_2x off 0 x2 45158400
i2s1 off 0 8 2822400
cdev1 on 1 22579200
alc5632 regs in 2.6.38:
cat /sys/kernel/debug/asoc/tegra-paz00/alc5632.0-001e/codec_reg
Initialization logs for 44100 KHz alc5632 (full log):
[ 118.721147] paz00_asoc_hw_params: input srate: 44100 [ 118.724580] paz00_asoc_hw_params: calculated mclk: 22579200 [ 118.727952] paz00_asoc_hw_params: corrected mclk: 22579200 [ 118.731316] tegra_asoc_utils_set_rate: set srate: 44100, mclk: 22579200 [ 118.734813] tegra_asoc_utils_set_rate: new_baseclock: 56448000, rate: 44100 [ 118.738375] clk_disable: name: cdev1 [ 118.741913] clk_disable: name: pll_a_out0 [ 118.745462] clk_disable: name: pll_a_out0 [ 118.748839] clk_disable: name: pll_a [ 118.752133] tegra_asoc_utils_set_rate: pll_a=new_base=56448000, pll_a_out0=mclk=22579200 [ 118.755670] clk_set_rate: name: pll_a, rate: 56448000 [ 118.759508] clk_set_rate: name: pll_a_out0, rate: 22579200 [ 118.763024] clk_enable: name: pll_a [ 118.766521] clk_enable: name: pll_a_out0 [ 118.769932] clk_enable: name: cdev1 [ 118.773299] clk_enable: name: pll_a_out0 [ 118.776635] clk_enable: name: i2c1 [ 118.779860] clk_enable: name: clk_m [ 118.783080] clk_disable: name: i2c1 [ 118.786198] clk_disable: name: clk_m [ 118.789211] alc5632_set_dai_sysclk: clk_id: 0, fgreq: 22579200 (Clocks after PP and dividers) [ 118.792474] clk_enable: name: i2c1 [ 118.795730] clk_enable: name: clk_m [ 118.799000] clk_disable: name: i2c1 [ 118.802109] clk_disable: name: clk_m [ 118.805238] get_coeff: rate 44100 [ 118.808340] alc5632 0-001e: alc5632_pcm_hw_params: sysclk=22579200,rate=44100,coeff=0x3075 [ 118.808352] clk_enable: name: i2c1 [ 118.811498] clk_enable: name: clk_m [ 118.814677] clk_disable: name: i2c1 [ 118.817621] clk_disable: name: clk_m [ 118.820430] clk_set_rate: name: i2s1, rate: 2822400
Initialization logs for 48 kHz
[21858.448055] paz00_asoc_hw_params: input srate: 48000 [21858.451106] paz00_asoc_hw_params: calculated mclk: 24576000 [21858.454251] paz00_asoc_hw_params: corrected mclk: 24576000 [21858.457353] tegra_asoc_utils_set_rate: set srate: 48000, mclk: 24576000 [21858.460542] tegra_asoc_utils_set_rate: new_baseclock: 73728000, rate: 48000 [21858.463679] clk_disable: name: cdev1 [21858.466819] clk_disable: name: pll_a_out0 [21858.470007] clk_disable: name: pll_a_out0 [21858.473117] clk_disable: name: pll_a [21858.476316] tegra_asoc_utils_set_rate: pll_a=new_base=73728000, pll_a_out0=mclk=24576000 [21858.479643] clk_set_rate: name: pll_a, rate: 73728000 [21858.483350] clk_set_rate: name: pll_a_out0, rate: 24576000 [21858.486857] clk_enable: name: pll_a [21858.490219] clk_enable: name: pll_a_out0 [21858.493511] clk_enable: name: cdev1 [21858.496750] clk_enable: name: pll_a_out0 [21858.499933] clk_enable: name: i2c1 [21858.503071] clk_enable: name: clk_m [21858.506297] clk_disable: name: i2c1 [21858.509416] clk_disable: name: clk_m [21858.512484] alc5632_set_dai_sysclk: clk_id: 0, fgreq: 24576000 (Clocks after PP and dividers) [21858.515801] clk_enable: name: i2c1 [21858.519022] clk_enable: name: clk_m [21858.522329] clk_disable: name: i2c1 [21858.525487] clk_disable: name: clk_m [21858.528626] get_coeff: rate 48000 [21858.531764] alc5632 0-001e: alc5632_pcm_hw_params: sysclk=24576000,rate=48000,coeff=0x3075 [21858.531776] clk_enable: name: i2c1 [21858.534963] clk_enable: name: clk_m [21858.538154] clk_disable: name: i2c1 [21858.541122] clk_disable: name: clk_m [21858.543966] clk_set_rate: name: i2s1, rate: 3072000
according to comment /* dap_mclk1, belongs to the cdev1 pingroup. */ - DAP_MCLK1 = cdev1 = MCLK
according to value (2822400) - DAP1_SCLK = i2s1 = BCLK (COULD BE WRONG)
/* We could un-tristate the cdev1 or cdev2 pingroup here; this is * currently done in the pinmux code. */
I found difference in dev1 clock initialization between our source tree and nv-tegra/trimslice. In our tree cdev1 have parent. In other trees it is have no parent and specified rate and max_rate. Is it matter ? ...
https://gitorious.org/trimslice-kernel/trimslice-kernel/blobs/master/arch/arm/mach-tegra/tegra2_clocks.c#line1705
https://gitorious.org/trimslice-kernel/trimslice-kernel/blobs/master/arch/arm/mach-tegra/board-trimslice.c#line235
vs
https://gitorious.org/~marvin24/ac100/marvin24s-kernel/blobs/chromeos-ac100-2.6.38/arch/arm/mach-tegra/board-paz00.c#line423
https://gitorious.org/~marvin24/ac100/marvin24s-kernel/blobs/chromeos-ac100-2.6.38/arch/arm/mach-tegra/tegra2_clocks.c#line1968